1. Field of the Invention
The present invention relates to a semiconductor device including a conductive layer buried in an opening formed in a semiconductor substrate or an insulator thereon, and a method of manufacturing the same.
2. Description of the Related Art
Device scale-down and high integration have advanced in a semiconductor integrated circuit. As a result, devices must be formed in a region having a small area with high density. For example, a semiconductor memory device such as CMOS dynamic random access memory (DRAM) having a large capacitance needs to increase the storage capacitance of memory devices effectively using the narrow region. In order to increase the storage capacitance, a trench capacitor using the side wall of a trench as a cell capacitor is employed. The trench capacitor has the following two structures. For example, according to one structure, a diffusion layer is formed in a substrate contacting with the trench, the diffusion layer is used as one of the capacitor electrode, and a storage electrode is buried in the trench via a capacitor insulating film. According to another structure, a substrate formed with a trench is used as one of the capacitor electrodes, that is, plate electrode, and a storage electrode is buried in the trench via a capacitor insulating film.
The trench capacitor is conventionally formed in the following manner. The following is an explanation about the process of manufacturing the trench capacitor having the latter structure. A trench is formed in a semiconductor substrate. The inner surface of the trench is formed with a capacitor insulating film. A first conductive material is further buried (filled) in the trench. Thereafter, recess etching is carried out so that the first conductive material remains in only lower portion of the trench. Then, a collar oxide film is deposited in the inner surface of the trench, and thereafter, the bottom portion of the collar oxide film is removed. A second conductive material is further buried in the trench. The first conductive material is used as the storage electrode and the second conductive material is used as the contact plug between the storage electrode and a third conductive material is buried above the second material.
When the cross section of the trench has a tapered shape, there is no problem. However, the aspect ratio of the trench becomes high resulting from device miniaturization, and thereby, it is difficult to control the sectional shape of the trench. For this reason, the side of the trench has the following sectional shapes. More specifically, the angle to the extended surface of the bottom surface of the trench is an approximately right angle, for example, 89° or more, that is, the side of the trench has a non-tapered shape. Further, the foregoing angle is 100° or more, that is, the side of the trench has an obtuse angle reverse tapered shape or acute angle overhang shape. In such a case, an empty space (cavity) is generated in the first conductive material, or a recess is generated on the upper surface of the first conductive material.
When the collar oxide film is deposited in the trench in the foregoing state, the bottom of the collar oxide film is buried in the cavity generated in the first conductive material or the recess on the upper surface thereof. Thereafter, when the bottom of the collar oxide film is etched, there is a possibility that an etching residual of the collar oxide film occurs. This is a factor of causing the following problem. When the second conductive material is deposited on the first conductive material in the post process, the connection state between the first and second conductive materials becomes non-uniform or insufficient. As a result, the resistance value of the storage electrode increases, and further, the connection state between the first and second conductive materials becomes a breaking state. Thus, open fail of the storage electrode occurs.
The same problem as the trench capacitor arises in the following case. More specifically, conductive materials such as metal and polycrystalline silicon are buried in an opening having high aspect ratio, formed an insulating layer on the semiconductor substrate, for example, contact or via opening, and plug is formed. In other words, when the cross section of the opening having high aspect ratio has a tapered shape, no problem arises. It is difficult to control the cross section of the opening to form a desired shape resulting from the influence of micro loading effect. When the cross section of the opening is formed into a vertical shape or a reverse tapered shape or overhang shape, coverage characteristic is worsened when the conductive material is buried (filled) in the opening. As a result, a cavity is generated in the conductive material, or a recess is formed on the upper surface of the conductive material. Thereafter, upper-layer interconnects are formed to contact with the surface of the conductive material. In this case, the problem arises in contact uniformity between the upper-layer interconnects and the conductive material and in flatness of interconnection layers.
U.S. Pat. No. 5,300,800 discloses a substrate plate type DRAM cell structure using a trench capacitor. U.S. Pat. No. 5,451,809 discloses a technique of etching back polysilicon buried in the trench, and forming a cap layer using amorphous silicon. U.S. Pat. No. 6,638,815 discloses a technique of burying (filling) amorphous silicon in the upper portion of a polysilicon electrode in the trench to form a trench capacitor. U.S. Pat. No. 6,359,300 discloses the following process technique. According to the process technique, silicon germanium is buried in the trench, and annealed, and thereby, a trench buried layer reducing thermal stress is formed. A collar oxide film is further formed, and thereafter, a conductive layer is buried.